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L6730C L6730D
Adjustable step-down controller with synchronous rectification
Target Specification
Features

Input voltage range from 1.8V to 14V Supply voltage range from 4.5V to 14V Adjustable output voltage down to 0.6V with 0.8% accuracy over line voltage and temperature (0C~125C) Fixed frequency voltage mode control TON lower than 100ns 0% to 100% duty cycle Selectable 0.6V or 1.2V internal voltage reference External input voltage reference Soft-start and inhibit High current embedded drivers Predictive anti-crossconduction control Selectable UVLO threshold (5V or 12V bus) Programmable high-side and low-side RDS(on) sense over-current-protection Switching frequency programmable from 100KHz to 1MHz Master/slave synchronization with 180 phase shift Pre-bias start up capability (L6730C) Selectable source/sink or source only capability after soft-start (L6730C) Selectable constant current or hiccup mode overcurrent protection after soft-start (L6730D)

HTSSOP20
QFN 4x4 24L
Power good output with programmable delay Over voltage protection with selectable latched/not-latched mode Thermal shut-down Package: HTSSOP20, QFN4x4 24L
Applications

High performance / high density DC-DC modules Low voltage distributed DC-DC niPOL converters DDR memory supply DDR memory bus termination supply
Order Codes
Part number L6730CQ L6730CQTR L6730C L6730CTR L6730D L6730DTR June 2006 Package QFN4x4 24L QFN4x4 24L HTSSOP20 HTSSOP20 HTSSOP20 HTSSOP20 Rev 2 Packing Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel 1/50
www.st.com 50
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
L6730C - L6730D
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 4 5
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 14 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multifunction pin (S/O/U L6730C) (CC/O/U L6730D) . . . . . . . . . . . . . . . . . . 25 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.14.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.14.2 No-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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L6730C - L6730D
Contents
6
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 6.2 6.3 6.4 6.5 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Two quadrant or one quadrant operation mode (L6730C) . . . . . . . . . . . . . . 34
7
L6730 Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 7.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 9 10
I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 POL Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Summary description
L6730C - L6730D
1
Summary description
The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of 0.8% or to 1.2V, when one of the internal references is used. It is also possible to use an external reference from 0V to 2.5V. The input voltage can range from 1.8V to 14V, while the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast switching to the external power section and the output current can be in excess of 20A, depending on the number of the external MOSFETs used. The PWM duty cycle can range from 0% to 100% with a minimum on-time (TON, MIN) lower than 100ns making possible conversions with very low duty cycle and very high switching frequency. The device provides voltage-mode control. It includes a 400KHz free-running oscillator that is adjustable from 100KHz to 1MHz. The error amplifier features a 10MHz gain-bandwidthproduct and 5V/s slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(on) of both the high-side and lowside MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. A leading edge adjustable blanking time is also available to avoid false over-current-protection (OCP) interventions in every application condition. It is possible to select the HICCUP mode or the constant current protection (L6730D) after the soft-start phase. During the soft-start phase a constant current protection is provided. It is possible to select (before the device turn-on) the sink-source or the source-only mode capability by acting on a multifunction pin (L6730C). The L6730C disables the sink mode capability during the soft-start in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730D can always sink current and so it can be used to supply the DDR Memory BUS termination. Other features are Master-Slave synchronization (with 180 phase shift), Power-Good with adjustable delay, over-voltage-protection, feed-back disconnection, selectable UVLO threshold (5V and 12V Bus) and thermal shutdown. The HTSSOP20 package allows the realization of really compact DC/DC converters.
4/50
L6730C - L6730D
Summary description
1.1
Figure 1.
Functional description
Block diagram
VCC=4.5V to14V
Vin=1.8V to14V
OCL PGOOD
OCH
VCCDR
LDO
SS/INH SYNCH OSC EAREF
BOOT
Monitor Protection and Ref
OSC
HGATE
Vo
PHASE
L6730C/D
PGOOD SINK/OVP/UVLO* + 0.6V - 1.2V + LGATE
PWM E/A
PGND
TMASK
MASKING TIME ADJUSTMENT
+
-
GND
FB
COMP
Note:
In the L6730D the multifunction pin is: CC/OVP/UVLO.
5/50
Electrical data
L6730C - L6730D
2
2.1
Table 1.
Electrical data
Maximum rating
Absolute maximum ratings
Parameter VCC to GND and PGND, OCH, PGOOD Value -0.3 to 18 0 to 6 0 to VBOOT - VPHASE BOOT PHASE VPHASE PHASE Spike, transient < 50ns (FSW = 500KHz) SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP, S/O/ U, TMASK, PGOODELAY, VCCDR OCH Pin PGOOD Pin OTHER PINS Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002 "Human Body Model" Acceptance Criteria: "Normal Performance" -0.3 to 24 -1 to 18 -3 +24 -0.3 to 6 1500 1000 2000 V V V Unit V V V V Symbol VCC
VBOOT - VPHASE Boot Voltage VHGATE - VPHASE VBOOT
2.2
Table 2.
Thermal data
Thermal data
Description Max. Thermal Resistance Junction to ambient Storage temperature range Junction operating temperature range Ambient operating temperature range HTSSOP20 50 QFN4x4 30 Unit C/W C C C
Symbol RthJA(1) TSTG TJ TA
-40 to +150 -40 to +125 -40 to +85
1. Package mounted on demoboard
6/50
L6730C - L6730D
Pin connections and functions
3
Figure 2.
Pin connections and functions
Pins connection (top view)
PGOO D D ELAY SY NCH
SINK/OVP/UVLO
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PGOO D V CC V CCD R LGA TE PGN D BOO T HG ATE PH ASE OCH O CL
TM ASK GN D FB CO MP SS/INH EAREF OSC
HTSSO P20
HTSSOP20
1. In the L6730D the multifunction pin is: CC/OVP/UVLO.
QFN 4x4 24L
Table 3.
Pin n.
Pins connection
Name Description Connecting a capacitor between this pin and ground a delay is introduced between the trigger of the internal PGOOD comparator and the external signal rising edge. No delay can be introduced on the falling edge of the PGOOD signal. The delay can be calculated with the following formula:
1
PGOOD DELAY
PGDelay = 0.5 C ( pF )
[ s]
2
SYNCH
It is a Master-Slave pin. Two or more devices can be synchronized by simply connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180 phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If it is not used the SYNCH pin can be left floating. With this pin it is possible: - To enable-disable the sink mode current capability after SS (L6730C); - To enable-disable the constant current OCP after SS (L6730D); - To enable-disable the latch mode for the OVP; - To set the UVLO threshold for the 5V BUS and 12V BUS. The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold.
SINK/OVP/UVLO L6730C 3 CC/OVP/UVLO L6730D
7/50
Pin connections and functions
L6730C - L6730D
Table 3.
Pins connection
By connecting this pin to VCCDR or ground it is possible to select two different values for the leading edge blanking time on the peak-over-current-protection. The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. All the internal references are referred to this pin. This pin is connected to the error amplifier inverting input. Connect it to Vout through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. This pin is connected to the error amplifier output and is used to compensate the voltage control loop. The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10A through the capacitor. This pin is also used to inhibit the device: when the voltage at this pin is lower than 0.5V the device is disabled. It is possible to set two internal references 0.6V / 1.2V or provide an external reference from 0V to 2.5V: > - VEAREF from 0% to 80% of VCCDR - External Reference
4
TMASK
5 6
GND FB
7
COMP
8
SS/INH
9
EAREF
> - VEAREF from 80% to 95% of VCCDR - VREF=1.2V > - VEAREF from 95% to 100% of VCCDR - VREF=0.6V An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. Connecting an external resistor from this pin to GND, the external frequency can be increased according with the following equation:
Fsw = 400 KHz +
9.88 106 ROSC ( K)
10
OSC
Connecting a resistor from this pin to VCCDR (5V), the switching frequency can be lowered according with the following equation:
3.01 10 7 Fsw = 400 KHz - ROSC ( K)
If the pin is left open, the switching frequency is 400 KHz. Normally this pin is at a voltage of 1.2V. In OVP the pin is pulled up to 4.5V (only in latched mode). Don't connect a capacitor from this pin to GND.
8/50
L6730C - L6730D
Table 3. Pins connection
Pin connections and functions
A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100A (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation: 11 OCL
I = IOCL R OCL 2 RDSonLS
VALLEY
Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the highfrequency noise related to the GND. Connect a capacitor only to a "clean" GND. A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-current-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100A current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The over-current threshold is given by the following equation:
IPEAK = IOCH R OCH RDSonHS
12
OCH
13
PHASE
This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. This pin is connected to the high-side MOSFET(s) gate. Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. This pin is connected to the low-side MOSFET(s) gate. 5V internally regulated voltage. It is used to supply the internal drivers and as a voltage reference. Filter it to ground with at least 1F ceramic cap. Supply voltage pin. The operative supply voltage range is from 4.5V to 14V. This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to VCCDR with a 10K resistor to obtain a logical signal.
14 15
HGATE BOOT
16 17 18 19 20
PGND LGATE VCCDR VCC PGOOD
9/50
L6730C - L6730D
Electrical characteristics
4
Electrical characteristics
VCC = 12V, TA = 25C unless otherwise specified
Table 4.
Symbol
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
VCC supply current VCC Stand By current ICC VCC quiescent current OSC = open; SS to GND OSC= open; HG = open, LG = open, PH=open 4.5 8.5 6.5 mA 10
Power-ON 5V BUS Turn-ON VCC threshold Turn-OFF VCC threshold 12V BUS Turn-ON VCC threshold Turn-OFF VCC threshold VIN OK Turn-ON VOCH threshold Turn-OFF VOCH threshold VOCH = 1.7V VOCH = 1.7V VOCH = 1.7V VOCH = 1.7V 4.0 3.6 8.3 7.4 1.1 0.9 4.2 3.8 8.6 7.7 1.25 1.05 4.4 4.0 8.9 V 8.0 1.47 1.27
VCCDR Regulation VCCDR voltage Soft Start and Inhibit ISS Oscillator fOSC fOSC,RT VOSC Initial Accuracy Total Accuracy Ramp Amplitude OSC = OPEN RT = 390K to VCCDR RT = 18K to GND 380 -15 2.1 400 420 15 KHz % V SS = 2V Soft Start Current SS = 0 to 0.5V 20 30 45 7 10 13 A VCC =5.5V to 14V IDR = 1mA to 100mA 4.5 5 5.5 V
Output Voltage (1.2V MODE) VFB Output Voltage 1.190 1.2 1.208 V
Output Voltage (0.6 MODE) VFB Output Voltage 0.597 0.6 0.603 V
10/50
L6730C - L6730D
Electrical characteristics
Table 4.
Symbol
Electrical characteristics
Parameter Test Condition Min. Typ. Max. Unit
Error Amplifier REAREF IFB Ext Ref Clamp VOFFSET GV GBWP SR Gate Drivers RHGATE_ON High Side Source Resistance VBOOT - VPHASE = 5V VBOOT - VPHASE = 5V VCCDR = 5V VCCDR = 5V 1.7 1.12 1.15 0.6 Error amplifier offset Open Loop Voltage Gain Gain-Bandwidth Product Slew-Rate Vref = 0.6V Guaranteed by design Guaranteed by design COMP = 10pF Guaranteed by design EAREF Input Resistance I.I. bias current Vs. GND VF = 0V 2.3 -5 100 10 5 +5 70 100 0.290 150 0.5 k A V mV dB MHz V/s
RHGATE_OFF High Side Sink Resistance RLGATE_ON Low Side Source Resistance
RLGATE_OFF Low Side Sink Resistance Protections IOCH IOCL OCH Current Source OCL Current Source
VOCH = 1.7V
90 90
100 100 120
110 110
% % mA
VFB Rising OVP Over Voltage Trip (VFB / VEAREF) VEAREF = 0.6V VFB Falling VEAREF = 0.6V IOSC Power Good Upper Threshold (VFB / VEAREF) Lower Threshold (VFB / VEAREF) VPGOOD PGOOD Voltage Low VFB Rising VFB Falling IPGOOD = -5mA 108 OSC Sourcing Current VFB > OVP Trip VOSC = 3V
117 30
110
112
% % V
88
90 0.5
92
11/50
Electrical characteristics
L6730C - L6730D
Table 5.
Symbol Oscillator fOSC
Thermal characterizations (VCC = 12V)
Parameter Test Condition Min Typ Max Unit
Initial Accuracy
OSC = OPEN; TJ=0C~ 125C
376
400
424
KHz
Output Voltage (1.2V MODE) VFB Output Voltage TJ = 0C~ 125C TJ = -40C~ 125C 1.188 1.185 1.2 1.2 1.212 1.212 V V
Output Voltage (0.6V MODE) VFB Output Voltage TJ = 0C~ 125C TJ = -40C~ 125C 0.596 0.593 0.6 0.6 0.605 0.605 V V
12/50
L6730C - L6730D
Device description
5
5.1
Device description
Oscillator
The switching frequency is internally fixed to 400KHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging an internal capacitor (FSW = 400KHz). This current can be varied using an external resistor (RT) connected between OSC pin and GND or VCCDR in order to change the switching frequency. Since the OSC pin is maintained at fixed voltage (typ. 1.2V), the frequency is increased (decreased) proportionally to the current sunk (sourced) from (into) the pin. In particular, connecting RT versus GND the frequency is increased (current is sunk from the pin), according to the following relationship:
Fsw = 400 KHz +
9.88 10 6 ROSC ( K)
(1)
Connecting RT to VCCDR the frequency is reduced (current is sourced into the pin), according to the following relationship:
Fsw = 400 KHz -
3.01 10 7 (2) ROSC ( K)
Switching frequency variation vs. RT is shown in Figure 3.. Figure 3. Switching frequency variation versus RT.
1500 1400 1300 1200 1100 1000 Fsw (KHz) 900 800 700 600 500 400 300 200 100 0 100 200 300 400 500 600 700 800 900 1000 Rosc (KOHM)
Rosc connected to GND
Rosc connected to Vccdr
13/50
Device description
L6730C - L6730D
5.2
Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the VCCDR pin (see Figure 4.).
Figure 4.
LDO block diagram.
4.5V/ 14V
LDO
5.3
Bypassing the LDO to avoid the voltage drop with low Vcc
The LDO can be by-passed, providing directly a 5V voltage to VCCDR. In this case Vcc and VCCDR pins must be shorted together as shown in Figure 5. VCCDR pin must be filtered with at least 1F capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for Tmask pin, S/O/U pin (L6730C) or CC/O/U pin (L6730D) and PGOOD pin (see Table 3: Pins connection). If Vcc 5V the internal LDO works in dropout with an output resistance of about 1. The maximum LDO output current is about 100mA and so the output voltage drop can be 100mV: to avoid this the LDO can be bypassed.
Figure 5.
Bypassing the LDO
14/50
L6730C - L6730D
Device description
5.4
Internal and external references
It is possible to set two internal references, 0.6V and 1.2V or provide an external reference from 0V to 2.5V. The maximum value of the external reference depends on the VCC : with VCC = 4V the clamp operates at about 2V (typ.), while with VCC greater than 5V the maximum external reference is 2.5V (typ.).

VEAREF from 0% to 80% of VCCDR - External reference > VEAREF from 80% to 95% of VCCDR - VREF = 1.2V > VEAREF from 95% to 100% of VCCDR - VREF = 0.6V >
Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered:

The minimum OVP threshold is set at 300mV; The under-voltage-protection doesn't work; The PGOOD signal remains low;
To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into the device (see Figure 6.). Finally it must be taken into account that the voltage at the EAREF pin is captured by the device at the start-up when Vcc is about 4V.
5.5
Figure 6.
Error amplifier
Error amplifier reference
VCCDR 0.6V EAREF 100K 2.5V 1.2V EXT
Error Amplifier Ref.
15/50
Device description
L6730C - L6730D
5.6
Soft start
When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35A and charges the capacitor up to 0.5V. After that it becomes 10A until the final charge value of approximately 4V (see Figure 7.).
Figure 7.
Device start-up: Voltage at the SS pin.
Vc c
Vcc Vin 4.2V or 8.6V 4V .2
15 .2 V 1.25V Vs s Vss V in
t
4 V
4V
0.5V 0.5VV 0 .5
t
16/50
L6730C - L6730D
Device description
The reference of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value: 0.6V or 1.2V. During the soft-start phase the converter works in closed loop. The L6730C can only source current during the soft-start phase in order to manage the prebias start-up applications. The L6730D can always sink current and so it can be used to supply the DDR Memory termination BUS. If an over current is detected during the soft-start phase, the device provides a constant-current-protection. In this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and thus, in case of high ripple current during the soft-start, the converter can start-up in any case, limiting the current (see section 4.5 Monitoring and protections) but not entering in HICCUP mode. The soft-start phase ends when Vss reaches 3.5V. After that the over-current-protection triggers the HICCUP mode (L6730C). With the L6730D there is the possibility to set the HICCUP mode or the constant current mode after the soft-start acting on the multifunction pin CC/O/U. With the L6730 the low-side MOSFET(s) management after soft-start phase depends on the S/O/U pin state (see related section). If the sink-mode is enabled the converter can sink current after softstart (see figure 9) while, if the sink-mode is disabled the converter never sinks current (see figure 10).. Figure 8. Sink-mode enabled: Inductor current during and after soft-start (L6730C).
VOUT VSS VCC IL
17/50
Device description
L6730C - L6730D
Figure 9.
Sink-mode disabled: Inductor current during and after soft-start (L6730C).
Vout
Vss
Vcc IL
During normal operation, if any under-voltage is detected on one of the two supplies (VCC, VIN), the SS pin is internally shorted to GND by an internal switch and so the SS capacitor is rapidly discharged. Two different turn-on UVLO thresholds can be set: 4.2V for 5V BUS and 8.6V for 12V BUS.
18/50
L6730C - L6730D
Device description
5.7
Driver section
The high-side and low-side drivers allow using different types of power MOSFETs (also multiple MOSFETs to reduce the RDS(on)), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration (see Figure 10.).
Figure 10. Dead times
The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control doesn't work when the high-side body diode is conducting because the phase node doesn't go negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates.
19/50
Device description
L6730C - L6730D
5.8
Monitoring and protections
The output voltage is monitored by the FB pin. If it is not within 10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by adding an external capacitor on PGDelay pin (see Table 3: Pins connection and Figure 11.); this can be useful to perform cascade sequencing. The delay can be calculated with the following formula:
PGDelay = 0.5 C ( pF ) [pF] (3)
Figure 11. PGOOD signal
The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference, the low-side driver is turned on. If the OVP notlatched mode has been set the low-side MOSFET is kept on as long as the over voltage is detected (see Figure 12.).If OVP latched-mode has been set the low-side MOSFET is turned on until Vcc is toggled (see Figure 13.). In case of latched-mode OVP the OSC pin is forced high (4.5V typ.) if an over voltage is detected. . Figure 12. OVP not latched
LGate
FB
OSC
20/50
L6730C - L6730D
Figure 13. OVP latched
Device description
LGate
OSC FB
It must be taken into account that there is an electrical network between the output terminal and the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If the converter can sink current, in the most of cases the low-side will be turned-on before the output voltage exceeds the over-voltage threshold, because the error amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the behaviour is the same, because the low-side is turned-on immediately. Instead, if the sink-mode is disabled, the low-side will be turned-on only when the over-voltage-protection (OVP) operates and not before, because the current can't be reversed. In this case a delay between the output voltage rising and the FB voltage rising can appear and the OVP can operate on late. The following two figures show an over-voltage event in case of sink enabled and disabled. The output voltage rises with a slope of 100mV/s, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause. Figure 14. OVP with sink enabled: the low-side MOSFET is turned-on in advance.
VOUT
109% VFB
LGate
21/50
Device description
L6730C - L6730D
Figure 15. OVP with sink disabled: delay on the OVP operation.
126% VOUT
VFB
LGate
The L6730D can always sink current and so the OVP will operate always in advance. The device realizes the over-current-protection (OCP) sensing the current both on the high-side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 3: Pins connection):

Peak Current Limit Valley Current Limit
The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after an adjustable masking time (see Chapter 5.10 on page 25). The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a fix masking time of about 400ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peakcurrent-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode (L6730C): the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10A and when the voltage at the SS pin reaches 0.5V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned-off (after the masking time and the internal delay) and returned-on at the next pwm cycle. The limit of this protection is that the Ton can't be less than masking time plus propagation delay (see Chapter 5.9: Adjustable masking time on page 25) because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-currentprotection is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned-on until the current is over the valley-current-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula:
I MAX = IVALLEY +
Vin - Vout TON , MIN (4) L
In constant current protection a current control loop limits the value of the error amplifier's output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 16. shows the behaviour of the device during an over current condition that persists also in the soft-start phase.
22/50
L6730C - L6730D
Figure 16. Constant current and Hiccup Mode during an OCP (L6730C). VSS
Device description
VCOMP
IL
Using the L6730D there is the possibility to set the constant-current-protection also after the soft-start. The following figures show the behaviour of the L6730D during an overcurrent event. Figure 17. Peak overcurrent-protection in constant-current-protection (L6730D).
VOUT
Peak th
IL
IOUT
TON
Figure 17. shows the intervention of the peak OCP: the high-side MOSFET(s) is turned-off when the current exceeds the OCP threshold. In this way the duty-cycle is reduced, the VOUT is reduced and so the maximum current can be fixed even if the output current is escalating. Figure 18. shows the limit of this protection: the on-time can be reduced only to the masking time and, if the output current continues to increase, the maximum current can increase too. Notice how the Vout remains constant even if the output current increases because the on-time cannot be reduced anymore.
23/50
Device description
L6730C - L6730D
Figure 18. Peak OCP in case of heavy overcurrent (L6730D).
VOUT
IL
IOUT
If the current is higher than the valley OCP threshold during the off-time, the high-side MOSFET(s) will not be turned-on. In this way the maximum current can be limited (Figure 19.). Figure 19. Valley OCP (L6730D).
VOUT
Valley th
IL
TOFF
TOFF
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L6730C - L6730D
Device description
During the constant-current-protection if the Vout becomes lower than 80% of the programmed value an UV (under-voltage) is detected and the device enters in HICCUP mode. The undervoltage-lock-out (UVLO) is adjustable by the multifunction pin (see Chapter 5.10 on page 25). It's possible to set two different thresholds:

4.2V for 5V Bus 8.6V for 12V Bus
Working with a 12V BUS, setting the UVLO at 8.6V can be very helpful to limit the input current in case of BUS fall.
5.9
Adjustable masking time
By connecting the masking-time pin to VCCDR or GND it is possible to select two different values for the peak -current-protection leading edge blanking time. This is useful to avoid any false OCP trigger due to spikes and oscillations generated at the turn-on of the high-side MOSFET(s). The amount of this noise depends a lot on the layout, MOSFETs, free-wheeling diode, switched current and input voltage. In case of good layout and medium current, the minimum masking time can be chosen, while in case of higher noise, it's better to select to maximum one. Connecting Tmask pin to VCCDR the masking time is about 400ns while connecting it to GND the resulting masking time is about 260ns.
5.10
Multifunction pin (S/O/U L6730C) (CC/O/U L6730D)
With this pin it is possible:

To enable-disable the sink-mode-current capability (L6730C) or the constant current protection (L6730D) at the end of the soft-start; To enable-disable the latch-mode for the OVP; To set the UVLO threshold for 5V BUS and 12V BUS.
Table 6 shows how to set the different options through an external resistor divider: Figure 20. External resistor
VCCDR R1 L6730/B S/O/U CC/O/U
R2
L6730C/D
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Device description
L6730C - L6730D
Table 6.
R1 N.C 11K 6.2K 4.3K 2.7K 1.8K 1.2K 0
S/O/U pin; CC/O/U pin
R2 0 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K N.C VSOU/VCCDR 0 0.2 0.3 0.4 0.5 0.6 0.7 1 UVLO 5V BUS 5V BUS 5V BUS 5V BUS 12V BUS 12V BUS 12V BUS 12V BUS OVP Not Latched Not Latched Latched Latched Not Latched Not Latched Latched Latched SINK CC Not Yes Not Yes Not Yes Not Yes
5.11
Synchronization
The presence of many converters on the same board can generate beating frequency noise. To avoid this it is important to make them operate at the same switching frequency. Moreover, a phase shift between different modules helps to minimize the RMS current on the common input capacitors. Figure 21. shows the results of two modules in synchronization. Two or more devices can be synchronized simply connecting together the SYNCH pins. The device with the higher switching frequency will be the Master while the other one will be the Slave. The Slave controller will increase its switching frequency reducing the ramp amplitude proportionally and then the modulator gain will be increased.
Figure 21. Synchronization.
PWM SIGNALS INDUCTOR CURRENTS
To avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization between two (or more) L6730, it's important to know in advance which the master is, it's timely to set its switching frequency at least 15% higher than the slave. Using an external clock signal (fEXT) to synchronize one or more devices that are working at a different switching frequency (fSW) it is recommended to follow the below formula:
f SW f EXT 1,3 f SW
The phase shift between master and slaves is approximately done 180.
26/50
L6730C - L6730D
Device description
5.12
Thermal shutdown
When the junction temperature reaches 150C 10C the device enters in thermal shutdown. Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an internal switch. The device does not restart until the junction temperature goes down to 120C and, in any case, until the voltage at the soft-start pin reaches 500mV.
5.13
Minimum on-time (TON, MIN)
The device can manage minimum on-times lower than 100ns. This feature comes from the control topology and from the particular over-current-protection system of the L6730C L6730D. In fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6730C - L6730D, neither for the over-current protection, given that during the off-time the valley-current-protection can operate. The first advantage related to this feature is the possibility to realize extremely low conversion ratios. Figure 22. shows a conversion from 14V to 0.5V at 820KHz with a TON of about 50ns. The on-time is limited by the turn-on and turn-off times of the MOSFETs.
Figure 22. 14V -> 0.5V@820KHz, 5A
50ns
27/50
Device description
L6730C - L6730D
5.14
Bootstrap anti-discharging system
This built-in system avoids that the voltage across the bootstrap capacitor becomes less than 3.3V. An internal comparator senses the voltage across the external bootstrap capacitor keeping it charged, eventually turning-on the low-side MOSFET for approximately 200ns. If the bootstrap capacitor is not enough charged the high-side MOSFET cannot be effectively turnedon and it will present a higher RDS(on). In some cases the OCP can be also triggered. It's possible to mention at least two application conditions during which the bootstrap capacitor can be discharged:
5.14.1 Fan's power supply
In many applications the FAN is a DC MOTOR driven by a voltage-mode DC/DC converter. Often only the speed of the MOTOR is controlled by varying the voltage applied to the input terminal and there's no control on the torque because the current is not directly controlled. Obviously the current has to be limited in case of overload or short-circuit but without stopping the MOTOR. With the L6730D the current can be limited without shutting down the system because a constant-current-protection is provided. In order to vary the MOTOR speed the output voltage of the converter must be varied. Both L6730C and L6730D have a dedicated pin called EAREF (see the related section) that allows providing an external reference to the noninverting input of the error-amplifier. In these applications the duty cycle depends on the MOTOR's speed and sometimes 100% has to be set in order to go at the maximum speed. Unfortunately in these conditions the bootstrap capacitor can not be recharged and the system cannot work properly. Some PWM controller limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this make worse the performance during the load transient. Thanks to the "bootstrap antidischarging system" the L6730X can work at 100% without any problem. The following picture shows the device behaviour when input voltage is 5V and 100% is set by the external reference. Figure 23. 100% duty cycle operation
TOFF
200ns
VOUT = 5V Vout=5V
IN Vin=5V
V
= 5V
LGate LGate FSW 6.3KHz
Fsw? 6.3KHz
28/50
L6730C - L6730D
Device description
5.14.2 No-sink at zero current operation
The L6730C can work in no-sink mode. If output current is zero the converter skip some pulses and works with a lower switching frequency. Between two pulses can pass a relatively long time (say 200-300s) during which there's no switching activity and the current into the inductor is zero. In this condition the phase node is at the output voltage and in some cases this is not enough to keep the bootstrap cap charged. For example, if Vout is 3.3V the voltage across the bootstrap cap is only 1.7V. The high-side MOSFET cannot be effectively turned-on and the regulation can be lost. Thanks to the "bootstrap anti-discharging system" the bootstrap cap is always kept charged. The following picture shows the behaviour of the device in the following conditions: 12V3.3V@0A. Figure 24. 12V -> 3.3V@0A in no-sink IL
Minimum Bootstrap Voltage
Pulse train
VPHASE
It can be observed that between two pulses trains the low-side is turned-on in order to keep the bootstrap cap charged.
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Application details
L6730C - L6730D
6
6.1
Application details
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (IL) between 20% and 30% of the maximum output current. The inductance value can be calculated with the following relationship:
L
Vin - Vout Vout (6) Fsw I L Vin
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 25. shows the ripple current vs. the output voltage for different values of the inductor, with Vin = 5V and Vin = 12V at a switching frequency of 400KHz. Figure 25. Inductor current ripple.
INDUCT O R CURRE NT RIP P L 8 7 6 5 4 3 2 1 0 0 1 2 3 4 O UT P UT V O L T AG E (V )
V in = 1 2 V , L = 1 u H
V in = 1 2 V , L = 2 u H V in = 5 V , L = 5 0 0 n H V in = 5 V , L = 1 .5 u H
Increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size.
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L6730C - L6730D
Application details
6.2
Output capacitors
The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored into the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
Vout ESR = Iout ESR (7)
Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas:
VoutCOUT =
Iout 2 L (8) 2 Cout (Vin, min D max - Vout )
VoutCOUT
Iout 2 L = 2 Cout Vout
(9)
Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6730C - L6730D is 100%. For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum COUT value can be set. The ESR and COUT values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula:
Vout = I L ( ESR +
1 ) 8 Cout Fsw
(10)
Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible.
6.3
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Irms = Iout D (1 - D)
(11)
Where D is the duty cycle. The equation reaches its maximum value, IOUT/2 with D = 0.5. The losses in worst case are:
P = ESR (0.5 Iout ) 2
(12)
31/50
Application details
L6730C - L6730D
6.4
Compensation network
The loop is based on a voltage mode control (Figure 26.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulsewidth modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/ VCOMP. This function has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC.
Figure 26. Compensation network
ZFB ZIN
The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fastest transient response (but always lower than fSW/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade slope and a phase margin greater than 45. To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
LC =
1 L Cout
(13)
ESR =
1 ESR Cout
(14)
Compensation network singularity frequencies:
P1 =
1 (15) C18 C19 R5 C +C 19 18 1 R5 C19
(17)
P 2 =
1 R4 C20
(16)
Z 1 =
Z 2 =
1 C20 (R3 + R4 )
(18)
32/50
L6730C - L6730D
Application details
Compensation network design: - Put the gain R5/R3 in order to obtain the desired converter bandwidth
C =
- - - - -
R5 Vin LC R3 Vosc
(18)
Place Z1 before the output filter resonance LC; Place Z2 at the output filter resonance LC; Place P1 at the output capacitor ESR zero ESR; Place P2 at one half of the switching frequency; Check the loop gain considering the error amplifier open loop gain.
Figure 27. Asymptotic bode plot of converter's open loop gain
33/50
Application details
L6730C - L6730D
6.5
Two quadrant or one quadrant operation mode (L6730C)
After the soft-start phase the L6730C can work in source only (one quadrant operation mode) or in sink/source (two quadrant operation mode), depending on the setting of the multifunction pin (see Chapter 5.10 on page 25). The choice of one or two quadrant operation mode is related to the application. One quadrant operation mode permits to have a higher efficiency at light load, because the converter works in discontinuous mode (see Figure 28.). Nevertheless in some cases, in order to maintain a constant switching frequency, it's preferable to work in two quadrants, even at light load. In this way the reduction of the switching frequency due to the pulse skipping is avoided. To parallel two or more modules is requested the one quadrant operation in order not to have current sinking between different converters. Finally the two quadrant operation allows faster recovers after negative load transient. For example, let's consider that the load current falls down from IOUT to 0A with a slew rate sufficiently greater than L/VOUT (where L is the inductor value). Even considering that the converter reacts instantaneously setting to 0% the duty-cycle, the energy 1/2*L*IOUT2 stored in the inductor will be transferred to the output capacitors, increasing the output voltage. If the converter can sink current this overvoltage can be faster eliminated.
Figure 28. Efficiency in discontinuous-current-mode and continuous-current-mode.
EFFIC IENC Y: D C M vs. CC M
0.7 0.6 E FF. (% 0.5 0.4 0.3 0.2 0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 OUTP UT CURRENT (A) E FFICIENCY DCM E FFICIENCY CCM
34/50
L6730C - L6730D
L6730 Demoboard
7
7.1
L6730 Demoboard
Description
L6730 demoboard realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5V to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of 30A. The switching frequency is set at 400 KHz (controller free-running FSW) but it can be increased up to 1MHz. A 7 positions dip-switch allows to select the UVLO threshold (5V or 12V Bus), the OVP intervention mode and the sink-mode current capability.
Figure 29. Demoboard picture.
Top side
Bottom side
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L6730 Demoboard
L6730C - L6730D
7.2
PCB layout
Figure 31. Power ground layer
Figure 30. Top layer
Figure 32. Signal ground layer
Figure 33. Bottom layer
36/50
L6730C - L6730D
L6730 Demoboard
Figure 34. Demoboard schematic
Table 7.
Demoboard part list
Value
820 0 N.C. 10 1% 100mW 11K 1% 100mW 6K2 1% 100mW 4K3 1% 100mW 2K7 1% 100mW 1K8 1% 100mW 1K2 1% 100mW 2K7 1% 100mW 1K Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD
Reference
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12
Manufacturer
Neohm Neohm
Package
SMD 0603 SMD 0603
Supplier
IFARCAD IFARCAD
37/50
L6730 Demoboard
L6730C - L6730D
Table 7.
Demoboard part list
Value
2K7 1% 100mW 1K 1% 100mW 1K 1% 100mW 4K7 1% 100mW N.C. 2.2 2.2 10K 1% 100mW N.C. N.C. 0 220nF 100nF 1nF. 100uF 20V 4.7uF 20V 10nF N.C. 47nF 1.5nF 4.7nF 330uF 6.3V N.C. 1.8uH 1N4148 STS1L30M STS12NH3LL STSJ100NH3LL L6730 DIP SWITCH 7 POS. Panasonic ST ST ST ST ST SMD SOT23 DO216AA SO8 SO8 HTSSOP20 ST IFARCAD STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics Kemet Kemet Kemet POSCAP 6TPB330M SMD 0603 SMD 0603 SMD 0603 SMD IFARCAD IFARCAD IFARCAD SANYO Neohm Kemet Kemet Kemet OSCON 20SA100M AVX Kemet SMD 0603 SMD 0603 SMD 0603 SMD 0603 RADIAL 10X10.5 SMA6032 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD SANYO IFARCAD IFARCAD Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD
Reference
R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 C1 C3-C7-C9-C15-C21 C2 C4-C6 C8 C10 C11 C12 C13 C14 C18-C19 C20 L1 D1 D2 Q1-Q2 Q4-Q5 U1 SWITCH
Manufacturer
Neohm Neohm Neohm Neohm
Package
SMD 0603 SMD 0603 SMD 0603 SMD 0603
Supplier
IFARCAD IFARCAD IFARCAD IFARCAD
38/50
L6730C - L6730D
Table 8. Other inductor manufacturer
Series 744318180 CDEP134-2R7MC-H HPI_13 T640 SPM12550T-1R0M220 FDA1254 HCF1305-1R0 COILTRONICS HC5-1R0 1.3 Inductor Value (H) 1.8 2.7 1.4 1 2.2 1.15
L6730 Demoboard
Manufacturer WURTH ELEKTRONIC SUMIDA EPCOS TDK TOKO
Saturation Current (A) 20 15 22 22 14 22 27
Table 9.
Other capacitor manufacturer
Series C4532X5R1E156M TDK C3225X5R0J107M 100 100 100 6.3 25 6.3 Capacitor value(F) 15 Rated voltage (V) 25
Manufacturer
NIPPON CHEMI-CON PANASONIC
25PS100MJ12 ECJ4YB0J107M
39/50
I/O Description
L6730C - L6730D
8
I/O Description
Figure 35. Demoboard
Table 10.
I/O Functions
Function The input voltage can range from 1.8V to 14V. If the input voltage is between 4.5V and 14V it can supply also the device (through the VCC pin) and in this case the pin 1 and 2 of the jumper G1 must be connected together. The output voltage is fixed at 3.3V but it can be changed by replacing the resistor R14 of the output resistor divider:
Symbol Input (VIN-GIN)
Output (VOUT-GOUT)
Vo = VREF (1 +
R16 ) R14
The over-current-protection limit is set at 15A but it can be changed by replacing the resistors R1 and R12 (see OCL and OCH pin in Table 3: Pins connection). VCC-GNDCC
Using the input voltage to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the VCC input (4.5-14V) and, in this case, jumper G1 must be left open.
An internal LDO provides the power into the device. The input of this stage is the VCC pin and the output (5V) is the Vccdr pin. The LDO can be bypassed, providing directly a 5V voltage from VCCDR and Gndcc. In this case the pins 1 and 3 of the jumper G1 must be shorted. This pin can be used as an input or as a test point. If all the jumper G2 pins are shorted, TP1 can be used as a test point of the voltage at the EAREF pin. If the pins 2 and 3 of G2 are connected together, TP1 can be used as an input to provide an external reference for the internal error amplifier (see section 4.3. Internal and external references). This test point is connected to the Tmask pin (see Table 3: Pins connection). This test point is connected to the S/O/U pin (see Chapter 5.10 on page 25).
VCCDR
TP1
TP2 TP3
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L6730C - L6730D
Table 10. I/O Functions
I/O Description
SYNCH PWRGD DIP SWITCH
This pin is connected to the synch pin of the controller (see Chapter 5.11 on page 26). This pin is connected to the PGOOD pin of the controller. Different positions of the dip switch correspond to different settings of the multifunction pin (S/O/U) (CC/O/U).
Table 11.
UVLO 5V 5V 5V 5V 12V 12V 12V 12V
Dip switch
OVP Not Latched Not Latched Latched Latched Not Latched Not Latched Latched Latched SINK CC Not Yes Not Yes Not Yes Not Yes Vsou/VCCDR 0 0.2 0.3 0.4 0.5 0.6 0.7 1 DIP SWITCH S7 S1-S7 S2-S7 S3-S7 S4-S7 S5-S7 S6-S7 S1 STATE A B C D E F G H
41/50
Efficiency
L6730C - L6730D
9
Efficiency
The following figures show the demoboard efficiency versus load current for different values of input voltage and switching frequency:
Figure 36. Demoboard efficiency 400KHz
Fsw=400KHz
95.00% EFFICIENCY 90.00% 85.00% 80.00% 75.00% 1 3 5 7 Iout (A) 9 11
VO = 3.3V
VIN = 5V
VIN = 12V
13
15
Figure 37. Demoboard efficiency 645KHz
Fsw=645KHz
95.00% EFFICIENCY 90.00% 85.00% 80.00% 75.00% 70.00% 1 3 5 7 Iout (A) 9 11
VO = 3.3V
VIN = 5V
VIN = 12V
13
15
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L6730C - L6730D
Figure 38. Demoboard efficiency 1MHz
Efficiency
Fsw=1MHz
VO = 3.3V
95.00% 90.00% EFFICIENCY 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% 1 3 5 7 Iout (A) 9 11 13 15
VIN = 5V
VIN = 12V
Figure 39. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL
12V-->3.3V
0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 0.88 0.87 3 5 7 9 11 13 15 17 19 OUTPUT CURRENT (A)
EFFICIENCY (%)
400KHz 700KHz 1MHz
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POL Demoboard
L6730C - L6730D
10
10.1
POL Demoboard
Description
A compact demoboard has been realized to manage currents in the range of 10-15A. Figure 36. shows the schematic and Table 9. the part list. Multi-layer-ceramic-capacitors (MLCCs) have been used on the input and the output in order to reduce the overall size.
Figure 40. Pol demoboard schematic.
Table 12.
Pol demoboard part list.
Value
1K8 10K N.C. 10 11K 1% 100mW 2K7 1% 100mW N.C. 0 3K 1% 100mW 4K7 1% 100mW Neohm Neohm Neohm Neohm Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD
Reference
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
Manufacturer
Neohm Neohm
Package
SMD 0603 SMD 0603
Supplier
IFARCAD IFARCAD
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L6730C - L6730D
Table 12.
R11 R12 R13 R14 R15 C1-C7 C6- C19-C20-C9 C2 C11 C12 C13 C8 C14 C3-C4-C5
POL Demoboard
Pol demoboard part list.
15 1% 100mW 4K7 1% 100mW 1K 1% 100mW 2.2 2.2 220nF 100nF 1nF N.C. 68nF 220pF 4.7uF 20V 6.8nF 15uF Kemet Kemet AVX Kemet TDK MLC C4532X5R1E156M SMD 0603 SMD0603 SMA6032 SMD 0603 SMD1812 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD Neohm Neohm Neohm Neohm Neohm Kemet Kemet Kemet SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD
C15-C16-C17-C18
100uF
PANASONIC MLC P/N ECJ4YBOJ107M
SMD 1210
IFARCAD
L1 D1 Q1 Q2 U1
1.8uH STS1L30M STS12NH3LL STSJ100NH3LL L6730
Panasonic ST ST ST ST
SMD DO216AA POWER SO8 POWER SO8 HTSSOP20
ST ST ST ST ST
Figure 41. Pol Demoboard efficiency
12V-->3.3V@400KHz
0.94 0.92 EFFICIENCY 0.9 0.88 0.86 0.84 0.82 1 3 5 7 9 11 OUTPUT CURRENT (A)
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Package mechanical data
L6730C - L6730D
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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L6730C - L6730D
Table 13.
DIM. Min A A1 A2 b c
D(1) D1
(3)
Package mechanical data
HTSSOP20 mechanical data
mm Typ Max 1.200 0.150 1.050 0.300 0.200 6.600 6.600 4.500 Min inch Typ Max 0.047 0.006 0.041 0.012 0.008 0.260 0.260 0.177
0.800 0.190 0.090 6.400 2.200 6.200 4.300 1.500 0.450
1.000
0.031 0.007 0.003 0.252 0.087 0.244 0.170 0.059
0.039
6.500 6.400 4.400 0.650 0.600 1.000
0.256 0.252 0.173 0.025 0.024 0.039
E
E1
(2)
E2(3)
e L L1 k aaa
0.750
0.018
0.030
0 min., 8 max. 0.100
0.004
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Intelead flash or protrusions shall not exceed 0.25mm per side. 3. The size of exposed pad is variable depending of leadframe design pad size. End user should verify "D1" and "E2" dimensions for each device application.
Figure 42. Package dimensions
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Package mechanical data
L6730C - L6730D
Table 14.
Dim
QFN 4mm x 4mm 24L mechanical data
mm Min Typ Max 1.00 0.00 0.18 3.9 1.95 3.9 1.95 0.50 0.40 0.60 15.7 0.05 0.30 4.1 2.25 4.1 2.25 0.0 7.1 153.5 76.8 153.5 76.8 19.7 23.6 Min inch Typ Max 39.4 2.0 11.8 161.4 88.6 161.4 88.6
A A1 b D D2 E E2 e L
Figure 43. Package dimensions
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L6730C - L6730D
Revision history
12
Revision history
Table 15.
Date 21-Dec-2005 07-Jun-2006
Revision history
Revision 1 2 Initial release. Added QFN package information, new template Changes
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L6730C - L6730D
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